1. Field of the Invention
The present invention relates to a semiconductor nonvolatile memory capable of electrically programming data, more particularly relates to an increase of speed of data programming and erasing.
2. Description of the Related Art
In a semiconductor nonvolatile memory such as a NAND type flash memory and DINOR type flash memory, data is programmed together for all memory cells connected to a selected word line.
Namely, page programming is carried out in units of word lines.
FIG. 1A and FIG. 1B are views of memory array structures in NAND type and DINOR type flash memories, respectively.
FIG. 1A is a view, for convenience, of a NAND type flash memory array where four memory cells are connected to one NAND string connected to one bit line.
In FIG. 1A, BL denote a bit line. A NAND string comprised of two selection transistors ST1 to ST2 and four memory cells MT1 to MT4 connected in series is connected to the bit line BL.
The selection transistors ST1 and ST2 are respectively controlled by selection gate lines SL1 and SL2. Memory cells MT1 to MT4 are respectively controlled by word lines WL1 to WL4.
FIG. 1B is a view, for convenience, of a DINOR type flash memory array where four memory transistors are connected to one sub-bit line connected to one main bit line.
In FIG. 1B, MBL denotes a main bit line and SBL denotes a sub-bit line. The main bit line MBL and the sub-bit line SBL are operationally connected via the selection transistor ST1 controlled by the selection gate line SL.
The sub-bit line SBL intersects four word lines WL1 to WL4. Four memory cells MT1 to MT4 are arranged at their intersections.
Further, in a semiconductor nonvolatile memory such as a NOR type flash memory, data is rewritten by erasing data in predetermined block units (for example, about 64 Kbytes), then programming data in the memory cells of the erased block.
FIG. 2 is a view of a memory array structure and biasing conditions at the time of erasing data in a general NOR type flash memory.
In the NOR type flash memory of FIG. 2, for convenience, memory cells MT11 to MT44 are arranged in the form of a matrix at the lattice positions of the four word lines WL1 to WL4 and the four bit lines BL1 to BL4.
Next, an explanation will be made of a data erasing operation in the NOR type flash memory of FIG. 2.
In the erasing of data, as shown in FIG. 2, all word lines WL1 to WL4 in the memory array of the block to be erased are placed at the ground level (0 V), all bit lines BL1 to BL4 are placed in a floating state, and an erasing voltage pulse of a high voltage (for example, 12 V) is applied to a common source line VSS.
As a result, the electrons stored in the memory cells are drained from the source side by a tunnel current at the time of programming data so the threshold voltage Vth of each memory cell changes from the 6 V to 7 V of the data programming state to 2 V to 3 V of the erasing state.
As stated above, in a semiconductor nonvolatile memory performing page programming in units of word line sectors such as a NAND type and DINOR type flash memory, the data is programmed together for all memory cells connected to the selected word line. However, in the memory cells connected to the selected word line, a difference occurs in the programming speed due to variations of size etc. derived from the manufacturing process.
FIG. 3 is a view of the difference of the programming speed between memory cells connected to the selected word line. In FIG. 3, an abscissa represents the required programming time for each memory cell (tPROG).
Further, the ordinate represents the number of memory cells (N), that is, the frequency of distribution of the number of memory cells corresponding to the abscissa tPROG (programming time).
As shown in FIG. 3, in a semiconductor nonvolatile memory performing page programming in units of word line sectors such as a NAND type flash memory, there is a difference in the required programming time tPROG between memory cells.
Taking such variations of the program speed into account, in a general NAND type flash memory etc., from the viewpoint of keeping the differences of the threshold voltage Vth at the time of programming small, the programming operation is carried out via a verify operation. A so-called "bit-by-bit" program/verify operation is carried out successively prohibiting programming from the programmed memory cells and repeatedly successively performing the program/verify operation until all of the memory cells finished being programmed.
However, as shown in FIG. 3, in the case of a general memory cell, the required programming time tPROG is the t0 in the figure, but there are very rare cases where there is a memory cell requiring a very long programming time tPROG, for example, t1 in the figure due to variations of the manufacturing processes etc.
In such a case, due to this very rare memory cell slow in programming, the number of the program/verify operations becomes very large, for example, 100 times or more. As a result, the time required for finishing the page programming also becomes very long.
FIG. 4 is a view of the sequence flow at the time of data programming in a semiconductor nonvolatile memory performing page programming in units of word line sectors such as the NAND type flash memory of the related art.
Below, an explanation will be made of the sequence flow of FIG. 4.
At step SF1, the data programming is commenced. First, at step SF2, the page program data is transferred to a data latch circuit provided for every bit line in the memory array.
Next, at step SF3, the number of times K of the program/verify operations is reset to 0, then a programming operation applying a program pulse (step SF4) and a veritfy/reading operation automatically setting the re-program data after the verify/reading (step SF5) are continuously carried out.
Next, at step SF6, end point detection to determine if all of the memory cells have finished being programmed is carried out by checking whether or not there are one or more unprogrammed memory cell remaining in the re-program data.
As a result, when the end point showing that all of the bits have finished being programmed is detected, the data programming is ended (step SF9).
On the other hand, when the end point showing that all of the bits have finished being programmed cannot be detected, the number of times K of the program/verify operation is incremented (step SF7) and it is checked if K is less than a predetermined number of times k0 (for example about 100 times) set in advance (step SF8).
When K is less than k0, the sequence flow of step SF4 to step SF8 is carried out again. When K reaches k0, it is decided that the data programming has failed (step SF10).
This predetermined number of times K0 of the program/verify operation becomes very large, for example 100 times or more, in the case of the NAND type flash memory of the related art due to the very rare memory cells with slow programming speeds. As a result, the time required for finishing the page programming becomes very long.
Further, in a semiconductor nonvolatile memory such as a NOR type flash memory, data is rewritten by erasing data in predetermined block units (for example about 64 Kbytes), then data is programmed in block units. However, there are differences in the erasing speed in the memory cells in the erased block unit due to variations of size etc. stemming from the manufacturing process.
FIG. 5 is a view of the difference of erasing speeds between memory cells in an erased block. In FIG. 5, the abscissa represents the erasing time (terase), that is, the required erasing time of each memory cell. Further, the ordinate represents the number of memory cells (N), that is, the frequency of distribution of the number of memory cells corresponding to the abscissa terase (erasing time).
As shown in FIG. 5, in a semiconductor nonvolatile memory erasing data in predetermined block units such as a NOR type flash memory, there is a difference in the required erasing time terase between memory cells.
Taking such variations of the erasing speed into account, in a general NOR type flash memory, the erasing operation is carried out via a verify operation. The erasing/verify operation is repeatedly carried out until the data of all memory cells in the erased block finishes being erased.
However, as shown in FIG. 5, in the case of a general memory cell, the required erasing time terase is the t0 in the figure, but there are very rare cases where there is a memory cell requiring a very long erasing time terase, i.e., requiring for example t1 or more in the figure, due to variations in the manufacturing process etc.
In such a case, due to this very rare memory cell slow in programming, the number of the erasing/verify operations becomes very large, for example 100 times to 1000 times or more. As a result, the time required for finishing the erasing operation becomes very long. Consequently, the time required for the rewriting of the data also becomes long.
Further, when the frequency of erasing/verify operations becomes very large due to the very rare memory cell with the slow erasing speed, the memory cells with the fast erasing speed are excessively erased and the threshold voltage Vth of the memory cells becomes depleted in state (Vth&lt;0). This becomes a cause of malfunctions.
FIG. 6 is a view of the sequence flow at the time of erasing data and programming data after this in a semiconductor nonvolatile memory rewriting data in predetermined block units such as a NOR type flash memory of the related art.
Below, an explanation will be made of the sequence flow of FIG. 6.
At step SF21, the data erasure is commenced. At step SF22, the number of times L of the erasing/verify operation is set to an initial "1", then an erasing operation applying an erasing pulse (step SF23) and a verify/reading operation (step SF24) are continuously carried out.
When as a result of the verify/reading operation of step SF24, the end point showing that all of the memory cells in the block have finished being erased is detected (step SF25), the data erasing is ended and the data programming operation of step SF101 is commenced.
On the other hand, when as a result of the verify/reading operation of step SF24, the end point showing that all of the memory cells in the block have finished being erased is not detected (step SF25), at step SF26, it is checked whether or not the number of times K of the erasing/verify operation is less than the predetermined number of times K0 (for example about 100 to 1000 times) set in advance.
When the number of times K of the erasing/verify operation is less than the set number of times k0, the number of times K of the erasing/verify operation is further incremented (step SF27) and the sequence flow of steps SF23 to SF27 is carried out again. When the number of times K of the erasing/verify operation reaches the set number of times K0, it is decided that the data erasure has failed (step SF28).
Next, when the end point showing that all of the memory cells have finished being erased can-be detected, the data programming is commenced.
First, at step SF101, the address Ar-NO of the memory cell is set to the initial "1" then the data is programmed in the memory cell in accordance with the content of the data (step SF102) and it is checked whether or not the address Ar-NO is the last address (step SF103).
When the address Ar-NO is not the last address, the address Ar-NO is further incremented (step SF104) and the sequence flow of steps SF102 to SF104 is carried out again. Then, when the address Ar-NO reaches the last address, the data programming is ended (step SF105) In the above sequence flow, the predetermined number of times K0 of the erasing/verlfy operation becomes very large, for example, about 100 times to 1000 times in the case of the NOR type flash memory of the related art due to the very rare memory cell with a slow erasing speed. As a result, the time required for finishing the erasing operation becomes very long. Consequently, the time required for rewriting the data becomes long. Further, memory cells with a very high erasing speed are excessively erased due to the memory cell with the slow erasing speed. This become a cause of malfunctions.